Digital Verification Engineer

SYSTEM VERILOG

TDK Polska sp. z o.o.
Mid
Online interview
Employment contract
Warsaw Szczecin

Project description

  • Work with design team to understand the design intent and bring up the verification plans and schedules
  • Develop test environment, test plan, and test cases based on design specification and verification requirements
  • Have a test plan review and verification reviews with the teams at every stage
  • Debug test cases and report verification result to achieve the expected code/functional coverage goal
  • Cooperate with cross-functional teams and coordinate priorities to achieve higher productivity
  • Take dedicated ownership to execute block level and chip level verification
  • Drive the development of behavioral models for analog/MEMS blocks


Who we're looking for?

  • MSEE with 10+years (or PhD with 7+years) of digital functional verification experience on complex SoC or mixed-signal ASIC product development or MSEE with 5+years (pr PhD with 2+years) of digital functional verification experience on complex SoC or mixed-signal ASIC product development
  • Proven teamwork skills
  • Excellent analytical and problem solving skills
  • Excellent oral and written communication skills
  • Conversant with some HDL languages such as Verilog, SystemVerilog
  • (nice to have) Experienced in real Number Modeling in SystemVerilog or VerilogAMS language for discrete -time behavioral models of analog blocks
  • Experienced with environment and flow build-up with OVM/UVM/VMM, Metric-Driven verification methodology
  • Experienced with Assertions like PSL or SVA etc
  • Experienced with simulation tools such as VCS, Xcelium or Questa
  • Experienced with scripting languages like Perl/Python/Tcl or Knowledge of scripting languages like Perl/Python/Tcl
  • (nice to have) Understanding assembly programming and firmware development
  • Experience leading a project and a technical team of employees and contractors according MSEE with 10+ years and PhD with 7+ years

Skills
MSEE
PhD
Verilog
SystemVerilog
Python
Healthcare
  • Healthcare package
Leisure package
  • Leisure package
Kitchen
  • Lunches

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