AMS Verification Engineer

SYSTEM VERILOG

TDK Polska sp. z o.o.
Mid
Online interview
Employment contract
Warsaw Szczecin

Project description

  • Work with design team to understand the design intent and bring up the verification plans and schedules
  • Develop test environment, test plan, and test cases based on design specification and verification requirements
  • Have a test plan review and verification reviews with the teams at every stage
  • Cooperate with cross-functional teams and coordinate priorities to achieve higher productivity
  • Take dedicated ownership to execute block level and chip level verification
  • Drive the development of behavioral models for analog/MEMS blocks


We offer

  • Employment under a contract of employment
  • Possibility of a professional development in an International company
  • Very good working atmosphere
  • A package of additional benefits (LuxMed, insurance, lunch card)

Who we're looking for?

  • MSEE with 5+ years (or PhD with 2+ years) of work experience on verification or analog design for mixed-signal ASIC products
  • Proven teamwork skills
  • Excellent analytical and problem solving skills
  • Excellent oral and written communication skills
  • Knowledge of most common analog circuits schematic
  • Knowledge of schematic entry tools
  • Knowledge of some HDL languages such as Verilog, SystemVerilog, VerilogA/VerilogAMS
  • Experienced with analog and digital simulators such as Spectre, AFS, Xcelium, Questa or VCS
  • Experienced in Real Number Modeling in SystemVerilog or VerilogAMS language for discrete-time behavioral models of analog blocks
  • (nice to have) Experienced with Assertions like PSL or SVA etc
  • (nice to have) Basic knowledge of OVM/UVM/VMM environments and methodology
  • (nice to have), Knowledge of scripting languages like Perl/Python/Tcl

Skills
MSEE
PhD
Verilog
SystemVerilog
VerilogAMS
Healthcare
  • Healthcare package
Leisure package
  • Leisure package
Kitchen
  • Lunches

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